English translation for "universal asynchronous receiver"

通用异步接收程序, 通用异步接收器

Related Translations:

asynchronous:  adj.1.时间不一致的，不同时的。2.【电学】异步的。

asynchronous starting:  非同步启动异步起动异步启动

asynchronous response:  异步响应异步应答

asynchronous activation:  非同步激动

asynchronous interface:  异步接口

asynchronous multiplexer:  异步多路复用器异步多路转换器异步多任务器

asynchronous moniker:  异步名字对象

asynchronous character:  异步字符

asynchronous condenser:  异步补尝机异步补偿机异步调相机异步调相器

asynchronous control:  异步控制

Example Sentences:

	1.	Uart universal asynchronous receiver transmitter 通用异步接收发送装置
	2.	Uart universal asynchronous receiver transmitter 通用异步接收发送装置
	3.	Universal asynchronous receiver transmitter 通用同步接收发送器
	4.	The bluetooth specification supports uart universal asynchronous receiver transmitter and usb transport mechanisms for bluetooth hci packets Bluetooth规范支持针对bluetooth hci数据分组的uart （通用异步接收器/传送器）和usb传输机制。
	5.	In the course of the design , critical technologies are applied , such as digital phase - locked loop , fast fourier transform algorithm , universal asynchronous receiver & transmitter , and so on . in the project , as a important component , the module of monitoring the buses " power quality takes a long time 在设计过程中，使用的关键技术有：使用cpld仿真多路sspc多种状态；在对汇流条电能质量的监测过程中采用频率跟踪技术? ?全数字锁相环；应用fpga技术使用fft运算进行谐波分析；通用异步收发器等技术。
	6.	In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future 第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga

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